The present disclosure relates to fabricating semiconductor devices. More particularly, the present disclosure relates to forming and cutting structures such as fins and nanowires.
Transistors, such as field effect transistors (FETs), are the basic elements of microelectronics and integrated circuits. There has been a continuous drive to scale down or shrink transistors and other semiconductor devices to increase density and improve processing performance. Methods of shrinking line-widths in lithographic processes have historically involved using greater-NA optics (numerical aperture), shorter exposure wavelengths, or interfacial media other than air (e.g., water immersion). As the resolution of conventional lithographic processes has approached theoretical limits, manufacturers have started to turn to double-patterning (DP) methods and other patterning techniques to overcome optical limitations to make increasingly smaller features.